Category: Journal Papers

 
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An Integrated Platform for Bio-Analysis and Drug Delivery

 

The advances in the microelectronics fabrication allow the strong appearance of micro-electro-mechanical systems known as MEMS. MEMS enable the fabrication of smaller devices that are manufactured using standard microfabrication techniques similar to the ones that are used to create computer silicon chips. Several MEMS devices including micro-reservoirs, micro-pumps, cantilevers, rotors, channels, valves, sensors, and other structures have been designed, fabricated and tested from using materials that have been demonstrated to be biocompatible. This paper reviews the status of Micro-electronic and MEMS systems that can be used for adaptive drug administration. It presents different components and describes a possible implementation. Finally it presents a prototype that is termed ipill which stands intelligent pill.

 

Seoud Amer, Wael Badawy, “An Integrated Platform for Bio-Analysis and Drug Delivery,” Current Pharmaceutical Biotechnology,, Volume 6, Issue 1, February 2005, pp. 57 – 64.

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An Efficient Architecture for a Lifted 2D Biorthogonal DWT

 

This paper presents a new algorithm for a 2D non-separable lifted bi-orthogonal wavelet transform. The algorithm is derived by factoring complementary pairs of wavelet transform 2D filters. The results are efficient architectures for real time signal processing, which do not require transpose memory for the 2D processing of data. The proposed architecture exploits in place implementation, inherit from the algorithm, and can take advantage of both vertical and horizontal parallelism in the direct implementation. The processing in our architecture is scheduled by carefully pipelining the lifted steps, which allows for up to four times faster processing than the direct implementation. The proposed architecture operates at high speed, consumes low power and has reduced computational complexity as compared to previously published filter and lifted based bi-orthogonal wavelet architectures.

 

Mehboob Alam , Wael Badawy, Vassil Dimitrov and Graham Jullien, “An Efficient Architecture for a Lifted 2D Biorthogonal DWT,” The Journal of VLSI Signal Processing , Volume 40, Issue 3, July 2005, pp. 335 – 342

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Analog IP Reuse in Nano Technologies, design and reuse

Analog IP Reuse in Nano Technologies

Sherif Hammouda, Hazem Said, Mohamed Dessouky, Mohamed Tawfik, Quang Nguyen, Wael Badawy, Hazem Abbas, Hussein Shaheen, “Analog IP Reuse in Nano Technologies, design and reuse,” April 6, 2006.

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A Proposed Hardware Reference Model for Spatial Transformation and Quantization in H.264,

 

This paper presents three Very Large Scale Integration prototypes to exploit spatial redundancy in the H.264 standard. The proposed architectures are: (1) forward 4 × 4 integer approximation of DCT transform and quantization, which is applied to all blocks of a frame, (2) the 4 × 4 Hadamard transform and quantization that is applied to the DC coefficients of the luma component when the macroblock is encoded in 16 × 16 intra prediction mode, and (3) the 2 × 2 Hadamard transform and quantization that is applied to the DC coefficients of the chroma component as a second level in the transformation hierarchy. The developed algorithms are adopted by the H.264 standard. A performance analysis shows that the architectures satisfy the real-time constraints required by different digital video applications.

 

I. Amer, W. Badawy, G. Jullien, “A Proposed Hardware Reference Model for Spatial Transformation and Quantization in H.264,” Elsevier Journal of Visual Communication and Image Representation, Volume 17, Issue 2, April 2006, Pages 533-552.

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A Computational Memory Architecture for MPEG-4 Applications with Mobile Devices

 

This paper presents a Computational Memory architecture for MPEG-4 applications with mobile devices. The proposed architecture is used for real-time block-based motion estimation, which is the most computational intensive task in the video encoder. It uses the exhaustive block-matching algorithm (EBMA) for motion estimation. The proposed architecture consists of embedded SRAMs and a number of block-matching units working in parallel to process video data while stored in the memory. The block-matching units access the embedded SRAMs simultaneously, which increases the speed of the architecture.

The architecture processes CIF format video sequences (i.e., the frame size is 352 × 288 pixels) with block size of 16 × 16 pixels and ±15 pixels search range. The proposed architecture has been designed, prototyped, and simulated for 0.18 μm TSMC CMOS technology. The simulation shows that the proposed architectures processes up to 126 CIF frames per second with clock frequency 100 MHz. The synthesized prototype of the proposed architecture includes 200 KB memory and it has an area of 33.75 mm2 and consumes 986.96 mW @100 MHz.

Mohammed Sayed , Wael Badawy, “A Computational Memory Architecture for MPEG-4 Applications with Mobile Devices,” Journal of VLSI Signal Processing Systems for Signal, Image and Video Technology – Special Issue on Digital and Computational Video , Vol. 42, No. 1, pp. 35-42, January 2006.

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An Affine Based Algorithm and SIMD Architecture for Video Compression with Low Bit-rate Applications

This paper presents a new affine-based algorithm and SIMD architecture for video compression with low bit rate applications. The proposed algorithm is used for mesh-based motion estimation and it is named mesh-based square-matching algorithm (MB-SMA). The MB-SMA is a simplified version of the hexagonal matching algorithm [1]. In this algorithm, right-angled triangular mesh is used to benefit from a multiplication free algorithm presented in [2] for computing the affine parameters. The proposed algorithm has lower computational cost than the hexagonal matching algorithm while it produces almost the same peak signal-to-noise ratio (PSNR) values. The MB-SMA outperforms the commonly used motion estimation algorithms in terms of computational cost, efficiency and video quality (i.e., PSNR). The MB-SMA is implemented using an SIMD architecture in which a large number of processing elements has been embedded with SRAM blocks to utilize the large internal memory bandwidth. The proposed architecture needs 26.9 ms to process one CIF video frame. Therefore, it can process 37 CIF frames/s. The proposed architecture has been prototyped using Taiwan Semiconductor Manufacturing Company (TSMC) 0.18-μm CMOS technology and the embedded SRAMs have been generated using Virage Logic memory compiler.

Published in:

Circuits and Systems for Video Technology, IEEE Transactions on  (Volume:16 ,  Issue: 4 )

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Mohammed Sayed , Wael Badawy, “An Affine Based Algorithm and SIMD Architecture for Video Compression with Low Bit-rate Applications“, IEEE Transactions on Circuits and Systems for Video Technology, Vol. 16, Issue 4, pp. 457-471, April 2006. Abstract

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A New Topology for a Current-mode Wheatstone Bridge

This paper presents a new topology for a current-mode Wheatstone bridge (CMWB) that uses an operational floating current conveyor (OFCC) as a basic building block. The proposed CMWB has been analyzed, simulated, implemented, and experimentally tested. The experimental results verify that the proposed CMWB outperforms existing CMWBs in terms of accuracy. A new CMWB linearization technique based on OFCC has been proposed, used, analyzed, and tested. The advantages of the proposed CMWB are fourfold. Firstly, it reduces the number of sensing passive elements; i.e., we can use two resistors instead of four and get the same performance as the traditional voltage-mode implementation. Secondly, we can apply the superposition principle without adding signal conditioning circuitry; therefore, the addition of sensor effects is possible. Thirdly, it has a higher common-mode cancellation. Finally, the proposed CMWB topology offers a significant improvement in accuracy compared to other CMWBs

Published in:

Circuits and Systems II: Express Briefs, IEEE Transactions on  (Volume:53 ,  Issue: 1 )

Yehya H. Ghallab, and Wael Badawy ” A New Topology for a Current-mode Wheatstone Bridge” IEEE Transaction on Circuit and System II, Volume 53, No.1, pp. 18-22, January 2006.

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The Operational Floating Current Conveyor and Its Application

A five-port general-purpose analog building block, termed as an Operational Floating Current Conveyor (OFCC), is described. The OFCC combines the features of current feedback operational amplifier, second-generation current conveyor and operational floating conveyor. An implementation scheme of the OFCC is described and its terminal operational characteristics are used to yield a working device. The OFCC is then used as a single block to realize the current conveyors (CCII+ and CCII-) as well as the four basic amplifiers (i.e., voltage, current, transconductance, and transresistance amplifiers). The applications of the OFCC are presented and discussed. In the field of the analog filter synthesis, we proposed a new active universal second order filter using OFCC. It has three inputs and one output employing two OFCC, two capacitors and three resistors and can realize lowpass, bandpass, highpass, notch, and all pass filters from the same configuration. The proposed universal filters offer the following advantageous features: using active elements for the same type (OFCC). No requirement for component matching or cancellation constraints, which makes the filter easier to design, orthogonal adjustment of ω0 and Q and the circuits have low sensitivity. The simulation and experimental results are obtained and discussed.

Read More: https://www.worldscientific.com/doi/abs/10.1142/S0218126606003118

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Yehya Ghallab, Wael Badawy, M. Abo El-Ella, and M. Elsaid, “The Operational Floating Current Conveyor and Its Application“, Journal of Circuits, Systems and Computers, Volume 15, No. 3, June 2006, pp. 351–372.

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DeFET: A Novel CMOS Electric-Field Sensor for Lab-on-a-Chip and Biomedical Applications

This paper presents a novel CMOS electric-field sensor, it is called the “differential electric-field sensitive field-effect transistor” (DeFET), which is based on a standard 0.18-mum Taiwan Semiconductor Manufacturing Company (TSMC) CMOS technology. The DeFET shows a sensitivity of 51.7 mV/(V/mum). This paper also describes the DeFET’s theory of operation in addition to the experimental and simulation results that confirm the DeFET’s theory of operation. Some applications of the DeFET in the area of lab on a chip and biomedical are also presented

Published in:

Sensors Journal, IEEE  (Volume:6 ,  Issue: 4 )

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CAVLC Encoder Design for Real-Time Mobile Video Applications

Abstract

This brief presents a new context-based adaptive variable length coding (CAVLC) architecture. The prototype is designed for the H.264/AVC baseline profile entropy coder. The proposed design offers area savings by reducing the size of the statistic buffer. The arithmetic table elimination technique further reduces the area. The split VLC tables simplify the process of bit-stream generation and also help in reducing some area. The proposed architecture is implemented on Xilinx Virtex II field-programmable gate array (2v3000fg676-4). Simulation result shows that the architecture is capable of processing common/quarter-common intermediate format frame sequences in real-time at a core speed of 50 MHz with 6.85-K logic gates.

Published in:

Circuits and Systems II: Express Briefs, IEEE Transactions on  (Volume:54 ,  Issue: 10 )

C. A. Rahman and W. Badawy, “CAVLC Encoder Design for Real-time Mobile Video Applications”, The IEEE Trans. on Circuits and Systems II, Oct. 2007 Vol 54, Issue: 10, pp. 873-877.
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