Category: Journal Papers

 
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An Affine Based Algorithm and SIMD Architecture for Video Compression with Low Bit-rate Applications

This paper presents a new affine-based algorithm and SIMD architecture for video compression with low bit rate applications. The proposed algorithm is used for mesh-based motion estimation and it is named mesh-based square-matching algorithm (MB-SMA). The MB-SMA is a simplified version of the hexagonal matching algorithm [1]. In this algorithm, right-angled triangular mesh is used to benefit from a multiplication free algorithm presented in [2] for computing the affine parameters. The proposed algorithm has lower computational cost than the hexagonal matching algorithm while it produces almost the same peak signal-to-noise ratio (PSNR) values. The MB-SMA outperforms the commonly used motion estimation algorithms in terms of computational cost, efficiency and video quality (i.e., PSNR). The MB-SMA is implemented using an SIMD architecture in which a large number of processing elements has been embedded with SRAM blocks to utilize the large internal memory bandwidth. The proposed architecture needs 26.9 ms to process one CIF video frame. Therefore, it can process 37 CIF frames/s. The proposed architecture has been prototyped using Taiwan Semiconductor Manufacturing Company (TSMC) 0.18-μm CMOS technology and the embedded SRAMs have been generated using Virage Logic memory compiler.

Published in:

Circuits and Systems for Video Technology, IEEE Transactions on  (Volume:16 ,  Issue: 4 )

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Mohammed Sayed , Wael Badawy, “An Affine Based Algorithm and SIMD Architecture for Video Compression with Low Bit-rate Applications“, IEEE Transactions on Circuits and Systems for Video Technology, Vol. 16, Issue 4, pp. 457-471, April 2006. Abstract

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A New Topology for a Current-mode Wheatstone Bridge

This paper presents a new topology for a current-mode Wheatstone bridge (CMWB) that uses an operational floating current conveyor (OFCC) as a basic building block. The proposed CMWB has been analyzed, simulated, implemented, and experimentally tested. The experimental results verify that the proposed CMWB outperforms existing CMWBs in terms of accuracy. A new CMWB linearization technique based on OFCC has been proposed, used, analyzed, and tested. The advantages of the proposed CMWB are fourfold. Firstly, it reduces the number of sensing passive elements; i.e., we can use two resistors instead of four and get the same performance as the traditional voltage-mode implementation. Secondly, we can apply the superposition principle without adding signal conditioning circuitry; therefore, the addition of sensor effects is possible. Thirdly, it has a higher common-mode cancellation. Finally, the proposed CMWB topology offers a significant improvement in accuracy compared to other CMWBs

Published in:

Circuits and Systems II: Express Briefs, IEEE Transactions on  (Volume:53 ,  Issue: 1 )

Yehya H. Ghallab, and Wael Badawy ” A New Topology for a Current-mode Wheatstone Bridge” IEEE Transaction on Circuit and System II, Volume 53, No.1, pp. 18-22, January 2006.

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The Operational Floating Current Conveyor and Its Application

A five-port general-purpose analog building block, termed as an Operational Floating Current Conveyor (OFCC), is described. The OFCC combines the features of current feedback operational amplifier, second-generation current conveyor and operational floating conveyor. An implementation scheme of the OFCC is described and its terminal operational characteristics are used to yield a working device. The OFCC is then used as a single block to realize the current conveyors (CCII+ and CCII-) as well as the four basic amplifiers (i.e., voltage, current, transconductance, and transresistance amplifiers). The applications of the OFCC are presented and discussed. In the field of the analog filter synthesis, we proposed a new active universal second order filter using OFCC. It has three inputs and one output employing two OFCC, two capacitors and three resistors and can realize lowpass, bandpass, highpass, notch, and all pass filters from the same configuration. The proposed universal filters offer the following advantageous features: using active elements for the same type (OFCC). No requirement for component matching or cancellation constraints, which makes the filter easier to design, orthogonal adjustment of ω0 and Q and the circuits have low sensitivity. The simulation and experimental results are obtained and discussed.

Read More: https://www.worldscientific.com/doi/abs/10.1142/S0218126606003118

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Yehya Ghallab, Wael Badawy, M. Abo El-Ella, and M. Elsaid, “The Operational Floating Current Conveyor and Its Application“, Journal of Circuits, Systems and Computers, Volume 15, No. 3, June 2006, pp. 351–372.

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DeFET: A Novel CMOS Electric-Field Sensor for Lab-on-a-Chip and Biomedical Applications

This paper presents a novel CMOS electric-field sensor, it is called the “differential electric-field sensitive field-effect transistor” (DeFET), which is based on a standard 0.18-mum Taiwan Semiconductor Manufacturing Company (TSMC) CMOS technology. The DeFET shows a sensitivity of 51.7 mV/(V/mum). This paper also describes the DeFET’s theory of operation in addition to the experimental and simulation results that confirm the DeFET’s theory of operation. Some applications of the DeFET in the area of lab on a chip and biomedical are also presented

Published in:

Sensors Journal, IEEE  (Volume:6 ,  Issue: 4 )

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CAVLC Encoder Design for Real-Time Mobile Video Applications

Abstract

This brief presents a new context-based adaptive variable length coding (CAVLC) architecture. The prototype is designed for the H.264/AVC baseline profile entropy coder. The proposed design offers area savings by reducing the size of the statistic buffer. The arithmetic table elimination technique further reduces the area. The split VLC tables simplify the process of bit-stream generation and also help in reducing some area. The proposed architecture is implemented on Xilinx Virtex II field-programmable gate array (2v3000fg676-4). Simulation result shows that the architecture is capable of processing common/quarter-common intermediate format frame sequences in real-time at a core speed of 50 MHz with 6.85-K logic gates.

Published in:

Circuits and Systems II: Express Briefs, IEEE Transactions on  (Volume:54 ,  Issue: 10 )

C. A. Rahman and W. Badawy, “CAVLC Encoder Design for Real-time Mobile Video Applications”, The IEEE Trans. on Circuits and Systems II, Oct. 2007 Vol 54, Issue: 10, pp. 873-877.
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A Simplified 8×8 Transformation And Quantization Real-Time Ip-Block For Mpeg-4 H.264/Avc Applications: A New Design Flow Approach

Abstract

Current multimedia design processes suffer from the excessively large time spent on testing new IP-blocks with references based on large video encoders specifications (usually several thousands lines of code). The appropriate testing of a single IP-block may require the conversion of the overall encoder from software to hardware, which is difficult to complete in the short time required by the competition-driven reduced time-to-market demanded for the adoption of a new video coding standard. This paper presents a new design flow to accelerate the conformance testing of an IP-block using the H.264/AVC software reference model. An example block of the simplified 8 × 8 transformation and quantization, which is adopted in FRExt, is provided as a case study demonstrating the effectiveness of the approach.

To Download A SIMPLIFIED 8 × 8 TRANSFORMATION AND QUANTIZATION REAL-TIME IP-BLOCK FOR MPEG-4 H.264/AVC APPLICATIONS: A NEW DESIGN FLOW APPROACH

 

Ihab Amer, Wael Badawy, Graham Jullien, Marco Mattavelli, And Robert Turney, “A Simplified 8×8 Transformation And Quantization Real-Time Ip-Block For Mpeg-4 H.264/Avc Applications: A New Design Flow Approach,” Journal of Circuits, Systems, and Computers Vol. 16, No. 6 (2007) 1011–1026

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High-Throughput Identification and Classification Algorithm for Leukemia Population Statistics

Abstract:
Early detection of leukemia and reduced risk to human health can result from interdisciplinary integration of image analysis with clinical experimental results. Image analysis relies on efficient and reliable processing algorithms to make quantitative judgments on image data. This article presents the design and implementation of an efficient and high-throughput leukemia cell count and cluster classification algorithm to automatically quantify leukemia population statistics in the field of view. The algorithm is divided into two stages: (1) the cell identification stage and (2) the cell classification and inspection stage. The cell identification stage accurately segments background and noise from foreground pixels. A boundary box is generated enclosing the foreground pixels identifying all isolated cells and cell clusters. The cell classification and inspection stage uses one-dimensional intensity profiles that behave as signature plots to segregate isolated cells from cell clusters and evaluate total count within each cluster. The designed algorithm is tested with a variety of leukemia cell images that vary in image acquisition conditions, image sizes, cell sizes, intensity distributions, and image quality. The proposed algorithm demonstrates good potential in processing both ideal and nonideal images with an average accuracy of 91% and average processing time of 3 s. The performance of the proposed algorithm in comparison to recently published algorithms and commercial image analysis tool further ascertains its robustness.

Brinda Prasad and Wael Badawy, “High-Throughput Identification and Classification Algorithm for Leukemia Population Statistics,” The Journal of Imaging Science and Technology 52(3), 2008.

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Video-based Automatic Incident Detection for Intelligent Transportation systems: The Outdoor Environmental Challenges

Video-based automatic incident detection (AID) systems are increasingly being used in intelligent transportation systems (ITS). Video-based AID is a promising method of incident detection. However, the accuracy of video-based AID is heavily affected by environmental factors such as shadows, snow, rain, and glare. This paper presents a review of the different work done in the literature to detect outdoor environmental factors, namely, static shadows, snow, rain, and glare. Once these environmental conditions are detected, they can be compensated for, and hence, the accuracy of alarms detected by video-based AID systems will be enhanced. Based on the presented review, this paper will highlight potential research directions to address gaps that currently exist in detecting outdoor environmental conditions. This will lead to an overall enhancement in the reliability of video-based AID systems and, hence, pave the road for more usage of these systems in the future. Last, this paper suggests new contributions in the form of new suggested algorithmic ideas to detect environmental factors that affect AID systems accuracy.

Published in:

Intelligent Transportation Systems, IEEE Transactions on  (Volume:9 ,  Issue: 2 )

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A Robust Video-Based Algorithm for Detecting Snow Movement in Traffic Scenes

Abstract

Video-based Automatic Incident Detection (AID) systems are widely deployed in many cities for detecting traffic incidents to provide smoother, safer and congestion free traffic flow. However, the accuracy of an AID system operating in an outdoor environment suffers from high false alarm rates due to environmental factors. These factors include snow movement, static shadow and static glare on the roads. In this paper, a robust real-time algorithm is proposed to detect snow movement in video streams to improve the rate of detection. This is done by having the AID system reducing its sensitivity in the areas that have snow movements. The feasibility of the proposed algorithm has been evaluated using traffic videos captured from several cameras at the City of Calgary.

Jun Cai, Mohamed Shehata, Wael Badawy, “A Robust Video-Based Algorithm for Detecting Snow Movement in Traffic Scenes”, The Journal of VLSI Signal Processing Systems for Signal, Image, and Video Technology, Special Issue on Signal Processing Systems, Volume 56, Numbers 2-3 / September, 2009, pp. 307-326.

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Towards an H.264/AVC HW/SW Integrated Solution: An Efficient VBSME Architecture

Abstract:

This paper presents an efficient real-time variable block size motion estimation architecture. The proposed architecture provides motion vectors for each 16 times 16 block and its 40 sub-blocks. The proposed architecture is a single-instruction multiple-data architecture integrated with embedded SRAMs on one chip. The architecture has been prototyped using Xilinx Virtex-4 XC4VSX35-10 field-programmable gate array. It processes 30-CIF fps using 71-MHz clock frequency. Its maximum clock frequencyuency is 187.7 MHz and the maximum throughput is 20 4CIF fps. The prototyped architecture has 175 k gates and 18 kbits embedded SRAM.

Published in:

Circuits and Systems II: Express Briefs, IEEE Transactions on  (Volume:55 ,  Issue: 9 )

Mohammed Sayed, Wael Badawy, and Graham Jullien, “Towards an H.264/AVC HW/SW Integrated Solution: An Efficient VBSME Architecture”, IEEE Transactions on Circuits and Systems II, Volume: 55, Issue: 9, pp. 912-916, Sept. 2008.