Category: Magazine

 
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RAPID PROTOTYPING OF DIGITAL SYSTEMS: A TUTORIAL APPROACH

 

By James O. Hamblen and Michael D. Furman, Kluwer Academic Publishers, 2000.

This book provides an exciting and chal- lenging laboratory component for an un- dergraduate student as well as design engineers working in industry. It intro- duces the field programmable logic device (FPLD) technology and logic synthesis us- ing CAD tools. The book is organized in 13 chapters as follows. Chapter 1 provides a tutorial for CAD tools that covers the de- sign entry, simulation, and hardware im- plementation using an FPLD. Chapter 2 provides an overview of the UP1 FPLD de- velopment board, where the features of the board are briefly described. Chapter 3 introduces the programmable logic tech- nology where the most common complex programmable logic device (CPLD) and field programmable gate array (FPGA) are presented. Chapter 4 is a tutorial to use both a hierarchical and sequential design with different examples. Chapter 5 de- scribes the UP1core library I/O functions. Chapter 6 introduces the use of VHDL for the synthesis of digital hardware. Chapter 7 describes a state machine that controls a virtual electric train system simulation with video output generated directly by the CPLD. Chapter 8 develops a VHDL model of a simple computer where a fetch, decode, and execute cycle is simulated.

CIRCUITS & DEVICES s NOVEMBER 2001

39 s

Chapter 9 describes how to design an FPLD-based digital system to output VGA video. Chapter 10 describes the PS/2 key- board operation and presents interface ex- amples for integration in designs on the UP1 board. Chapter 11 describes the PS/2 mouse operation and presents interface examples for integration in designs on the UP1 board. Chapter 12 develops a design for an adaptable mobile robot using the UP1 board. Chapter 13 describes a single clock cycle model of the MIPS RISC pro- cessor. The book also includes a large number of laboratory problems and a vari- ety of design projects at the end of each chapter.

The book comes with the new student version of Altera’s MAX+PLUS II CAD tool and the UP1 board is available from Altera at special student pricing.

This is an ideal book for undergraduate digital logic and computer design courses with more than 40 fully developed and simulated examples that can be used on the UP1 board.

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Build a Hardware Accelerator

 

 

Amir Darvishi, Wael Badawy “Build a Hardware Accelerator“Circuit Cellar August 2005, pp.24 – 29

 

+

RAPID PROTOTYPING OF DIGITAL SYSTEMS: A TUTORIAL APPROACH

 

By James O. Hamblen and Michael D. Furman, Kluwer Academic Publishers, 2000.

This book provides an exciting and chal- lenging laboratory component for an un- dergraduate student as well as design engineers working in industry. It intro- duces the field programmable logic device (FPLD) technology and logic synthesis us- ing CAD tools. The book is organized in 13 chapters as follows. Chapter 1 provides a tutorial for CAD tools that covers the de- sign entry, simulation, and hardware im- plementation using an FPLD. Chapter 2 provides an overview of the UP1 FPLD de- velopment board, where the features of the board are briefly described. Chapter 3 introduces the programmable logic tech- nology where the most common complex programmable logic device (CPLD) and field programmable gate array (FPGA) are presented. Chapter 4 is a tutorial to use both a hierarchical and sequential design with different examples. Chapter 5 de- scribes the UP1core library I/O functions. Chapter 6 introduces the use of VHDL for the synthesis of digital hardware. Chapter 7 describes a state machine that controls a virtual electric train system simulation with video output generated directly by the CPLD. Chapter 8 develops a VHDL model of a simple computer where a fetch, decode, and execute cycle is simulated.

CIRCUITS & DEVICES s NOVEMBER 2001

39 s

Chapter 9 describes how to design an FPLD-based digital system to output VGA video. Chapter 10 describes the PS/2 key- board operation and presents interface ex- amples for integration in designs on the UP1 board. Chapter 11 describes the PS/2 mouse operation and presents interface examples for integration in designs on the UP1 board. Chapter 12 develops a design for an adaptable mobile robot using the UP1 board. Chapter 13 describes a single clock cycle model of the MIPS RISC pro- cessor. The book also includes a large number of laboratory problems and a vari- ety of design projects at the end of each chapter.

The book comes with the new student version of Altera’s MAX+PLUS II CAD tool and the UP1 board is available from Altera at special student pricing.

This is an ideal book for undergraduate digital logic and computer design courses with more than 40 fully developed and simulated examples that can be used on the UP1 board.

+

Build a Hardware Accelerator

 

 

Amir Darvishi, Wael Badawy “Build a Hardware Accelerator“Circuit Cellar August 2005, pp.24 – 29