Category: Journal Papers
CAVLC Encoder Design for Real-Time Mobile Video Applications
Abstract
This brief presents a new context-based adaptive variable length coding (CAVLC) architecture. The prototype is designed for the H.264/AVC baseline profile entropy coder. The proposed design offers area savings by reducing the size of the statistic buffer. The arithmetic table elimination technique further reduces the area. The split VLC tables simplify the process of bit-stream generation and also help in reducing some area. The proposed architecture is implemented on Xilinx Virtex II field-programmable gate array (2v3000fg676-4). Simulation result shows that the architecture is capable of processing common/quarter-common intermediate format frame sequences in real-time at a core speed of 50 MHz with 6.85-K logic gates.
Published in:
Circuits and Systems II: Express Briefs, IEEE Transactions on (Volume:54 , Issue: 10 )
- Page(s):
- 873 – 877
- ISSN :
- 1549-7747
- INSPEC Accession Number:
- 9633945
- DOI:
- 10.1109/TCSII.2007.902215
- Date of Publication :
- Oct. 2007
- Date of Current Version :
- 15 October 2007
- Issue Date :
- Oct. 2007
- Sponsored by :
- IEEE Circuits and Systems Society
- Publisher:
- IEEE
C. A. Rahman and W. Badawy, “CAVLC Encoder Design for Real-time Mobile Video Applications”, The IEEE Trans. on Circuits and Systems II, Oct. 2007 Vol 54, Issue: 10, pp. 873-877.
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A Simplified 8×8 Transformation And Quantization Real-Time Ip-Block For Mpeg-4 H.264/Avc Applications: A New Design Flow Approach
Abstract
Current multimedia design processes suffer from the excessively large time spent on testing new IP-blocks with references based on large video encoders specifications (usually several thousands lines of code). The appropriate testing of a single IP-block may require the conversion of the overall encoder from software to hardware, which is difficult to complete in the short time required by the competition-driven reduced time-to-market demanded for the adoption of a new video coding standard. This paper presents a new design flow to accelerate the conformance testing of an IP-block using the H.264/AVC software reference model. An example block of the simplified 8 × 8 transformation and quantization, which is adopted in FRExt, is provided as a case study demonstrating the effectiveness of the approach.
Ihab Amer, Wael Badawy, Graham Jullien, Marco Mattavelli, And Robert Turney, “A Simplified 8×8 Transformation And Quantization Real-Time Ip-Block For Mpeg-4 H.264/Avc Applications: A New Design Flow Approach,” Journal of Circuits, Systems, and Computers Vol. 16, No. 6 (2007) 1011–1026
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High-Throughput Identification and Classification Algorithm for Leukemia Population Statistics
Abstract:
Early detection of leukemia and reduced risk to human health can result from interdisciplinary integration of image analysis with clinical experimental results. Image analysis relies on efficient and reliable processing algorithms to make quantitative judgments on image data. This article presents the design and implementation of an efficient and high-throughput leukemia cell count and cluster classification algorithm to automatically quantify leukemia population statistics in the field of view. The algorithm is divided into two stages: (1) the cell identification stage and (2) the cell classification and inspection stage. The cell identification stage accurately segments background and noise from foreground pixels. A boundary box is generated enclosing the foreground pixels identifying all isolated cells and cell clusters. The cell classification and inspection stage uses one-dimensional intensity profiles that behave as signature plots to segregate isolated cells from cell clusters and evaluate total count within each cluster. The designed algorithm is tested with a variety of leukemia cell images that vary in image acquisition conditions, image sizes, cell sizes, intensity distributions, and image quality. The proposed algorithm demonstrates good potential in processing both ideal and nonideal images with an average accuracy of 91% and average processing time of 3 s. The performance of the proposed algorithm in comparison to recently published algorithms and commercial image analysis tool further ascertains its robustness.
Brinda Prasad and Wael Badawy, “High-Throughput Identification and Classification Algorithm for Leukemia Population Statistics,” The Journal of Imaging Science and Technology 52(3), 2008.
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Video-based Automatic Incident Detection for Intelligent Transportation systems: The Outdoor Environmental Challenges
Video-based automatic incident detection (AID) systems are increasingly being used in intelligent transportation systems (ITS). Video-based AID is a promising method of incident detection. However, the accuracy of video-based AID is heavily affected by environmental factors such as shadows, snow, rain, and glare. This paper presents a review of the different work done in the literature to detect outdoor environmental factors, namely, static shadows, snow, rain, and glare. Once these environmental conditions are detected, they can be compensated for, and hence, the accuracy of alarms detected by video-based AID systems will be enhanced. Based on the presented review, this paper will highlight potential research directions to address gaps that currently exist in detecting outdoor environmental conditions. This will lead to an overall enhancement in the reliability of video-based AID systems and, hence, pave the road for more usage of these systems in the future. Last, this paper suggests new contributions in the form of new suggested algorithmic ideas to detect environmental factors that affect AID systems accuracy.
Published in:
Intelligent Transportation Systems, IEEE Transactions on (Volume:9 , Issue: 2 )
- Page(s):
- 349 – 360
- ISSN :
- 1524-9050
- INSPEC Accession Number:
- 10034942
- DOI:
- 10.1109/TITS.2008.915644
- Date of Publication :
- June 2008
- Date of Current Version :
- 06 June 2008
- Issue Date :
- June 2008
- Sponsored by :
- IEEE Intelligent Transportation Systems Society
- Publisher:
- IEEE
Mohamed Shehata, Jun Cai, Muzamil Pervez, Tyson Burr, Wael Badawy, Ahmad Radmanesh, “Video-based Automatic Incident Detection for Intelligent Transportation systems: The Outdoor Environmental Challenges“, the IEEE Transactions on Intelligent Transportation Systems, Volume: 9, Issue: 2, pp. 349-360, June 2008.
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A Robust Video-Based Algorithm for Detecting Snow Movement in Traffic Scenes
Abstract
Video-based Automatic Incident Detection (AID) systems are widely deployed in many cities for detecting traffic incidents to provide smoother, safer and congestion free traffic flow. However, the accuracy of an AID system operating in an outdoor environment suffers from high false alarm rates due to environmental factors. These factors include snow movement, static shadow and static glare on the roads. In this paper, a robust real-time algorithm is proposed to detect snow movement in video streams to improve the rate of detection. This is done by having the AID system reducing its sensitivity in the areas that have snow movements. The feasibility of the proposed algorithm has been evaluated using traffic videos captured from several cameras at the City of Calgary.
Jun Cai, Mohamed Shehata, Wael Badawy, “A Robust Video-Based Algorithm for Detecting Snow Movement in Traffic Scenes”, The Journal of VLSI Signal Processing Systems for Signal, Image, and Video Technology, Special Issue on Signal Processing Systems, Volume 56, Numbers 2-3 / September, 2009, pp. 307-326.
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Towards an H.264/AVC HW/SW Integrated Solution: An Efficient VBSME Architecture
Abstract:
This paper presents an efficient real-time variable block size motion estimation architecture. The proposed architecture provides motion vectors for each 16 times 16 block and its 40 sub-blocks. The proposed architecture is a single-instruction multiple-data architecture integrated with embedded SRAMs on one chip. The architecture has been prototyped using Xilinx Virtex-4 XC4VSX35-10 field-programmable gate array. It processes 30-CIF fps using 71-MHz clock frequency. Its maximum clock frequencyuency is 187.7 MHz and the maximum throughput is 20 4CIF fps. The prototyped architecture has 175 k gates and 18 kbits embedded SRAM.
Published in:
Circuits and Systems II: Express Briefs, IEEE Transactions on (Volume:55 , Issue: 9 )
- Page(s):
- 912 – 916
- ISSN :
- 1549-7747
- INSPEC Accession Number:
- 10185530
- DOI:
- 10.1109/TCSII.2008.923398
- Date of Publication :
- 23 May 2008
- Date of Current Version :
- 29 August 2008
- Issue Date :
- Sept. 2008
- Sponsored by :
- IEEE Circuits and Systems Society
- Publisher:
- IEEE
Mohammed Sayed, Wael Badawy, and Graham Jullien, “Towards an H.264/AVC HW/SW Integrated Solution: An Efficient VBSME Architecture”, IEEE Transactions on Circuits and Systems II, Volume: 55, Issue: 9, pp. 912-916, Sept. 2008.
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An Architecture for Programmable Multi-core IP Accelerated Platform with an Advanced Application of H.264 Codec Implementation
Abstract
A new integrated programmable platform architecture is presented, with the support of multiple accelerators and extensible processing cores. An advanced application for this architecture is to facilitate the implementation of H.264 baseline profile video codec. The platform architecture employs the novel concept of virtual socket and optimized memory access to increase the efficiency for video encoding. The proposed architecture is mapped on an integrated FPGA device, Annapolis WildCard-II™ or WildCard-4™, for verification. According to the evaluation under different configurations, the results show that the overall performance of the architecture, with the integrated accelerators, can sufficiently meet the real-time encoding requirement for H.264 BP at basic levels, and achieve about 2–5.5 and 1–3 dB improvement, in terms of PSNR, as compared with MPEG-2 MP and MPEG-4 SP, respectively. The architecture is highly extensible, and thus can be utilized to benefit the development of multi-standard video codec beyond the description in this paper.
Yifeng Qiu, Wael Badawy and Robert Turney, “An Architecture for Programmable Multi-core IP Accelerated Platform with an Advanced Application of H.264 Codec Implementation” Journal of Signal Processing Systems, Volume 57, Number 2 / November, 2009, 123-137.
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Interpolation-Free Fractional-Pixel Motion Estimation Algorithms with Efficient Hardware Implementation`
A Prototyping Virtual Socket System-On-Platform Architecture with a Novel ACQPPS Motion Estimator for H.264 Video Encoding Applications
Abstract
H.264 delivers the streaming video in high quality for various applications. The coding tools involved in H.264, however, make its video codec implementation very complicated, raising the need for algorithm optimization, and hardware acceleration. In this paper, a novel adaptive crossed quarter polar pattern search (ACQPPS) algorithm is proposed to realize an enhanced inter prediction for H.264. Moreover, an efficient prototyping system-on-platform architecture is also presented, which can be utilized for a realization of H.264 baseline profile encoder with the support of integrated ACQPPS motion estimator and related video IP accelerators. The implementation results show that ACQPPS motion estimator can achieve very high estimated image quality comparable to that from the full search method, in terms of peak signal-to-noise ratio (PSNR), while keeping the complexity at an extremely low level. With the integrated IP accelerators and optimized techniques, the proposed system-on-platform architecture sufficiently supports the H.264 real-time encoding with the low cost.
Yifeng Qiu and Wael Badawy, “A Prototyping Virtual Socket System-On-Platform Architecture with a Novel ACQPPS Motion Estimator for H.264 Video Encoding Applications” EURASIP Journal on Embedded Systems, Volume 2009
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Efficient Variable Block Size Selection for AVC Low Bitrate Applications
ABSTRACT
The Advanced Video Coding (AVC) standard proposes the usage of Variable Block Size (VBS) motion-compensated prediction and mode decision aiming for an optimized Rate-Distortion (R-D) performance. Unlike Fixed Block Size (FBS) motion-compensated prediction, where all regions of the pictures are treated similarly in terms of temporal prediction, VBS increases the efficiency of encoding by allowing more active regions to be represented with more bits than less active ones. The main concern regarding the usage of VBS motion-compensated prediction is the dramatic increase it adds to the encoder computational requirements, which not only prevents the encoder from satisfying real-time constraints, but also makes it impractical for hardware implementation. This paper presents an efficient VBS selection scheme, which can be applied to any VBS Motion Estimation (ME) module, leading to significant reduction in its computational requirements with minor loss in the quality of the reconstructed picture. The computational requirements reduction is achieved by minimizing the number of required ME searches and simplifying the Mode Decision (MD) operation. In order to meet different applications’ demands, the proposed algorithm can be adjusted to function at any of three operating points, trading off computational requirements with R-D performance. In the paper, the algorithm is described in detail, focusing on the theoretical computational requirements savings. This theoretical analysis is then supported with simulation results performed on three benchmark video sequences with various types of motion. Keywords-H.264/AVC, motion estimation, variable block size.
Reference: Ihab Amer, Wael Badawy, Graham Jullien, Adrian Chirila-Rus, Robert Turney, and Rana Hamed, “Efficient Variable Block Size Selection for AVC Low Bitrate Applications,” IARIA on-line journals, 2010 Vol. 1&2, July 2010.
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