Towards an H.264/AVC HW/SW Integrated Solution: An Efficient VBSME Architecture
This paper presents an efficient real-time variable block size motion estimation architecture. The proposed architecture provides motion vectors for each 16 times 16 block and its 40 sub-blocks. The proposed architecture is a single-instruction multiple-data architecture integrated with embedded SRAMs on one chip. The architecture has been prototyped using Xilinx Virtex-4 XC4VSX35-10 field-programmable gate array. It processes 30-CIF fps using 71-MHz clock frequency. Its maximum clock frequencyuency is 187.7 MHz and the maximum throughput is 20 4CIF fps. The prototyped architecture has 175 k gates and 18 kbits embedded SRAM.
Circuits and Systems II: Express Briefs, IEEE Transactions on (Volume:55 , Issue: 9 )
- 912 – 916
- ISSN :
- INSPEC Accession Number:
- Date of Publication :
- 23 May 2008
- Date of Current Version :
- 29 August 2008
- Issue Date :
- Sept. 2008
- Sponsored by :
- IEEE Circuits and Systems Society
Mohammed Sayed, Wael Badawy, and Graham Jullien, “Towards an H.264/AVC HW/SW Integrated Solution: An Efficient VBSME Architecture”, IEEE Transactions on Circuits and Systems II, Volume: 55, Issue: 9, pp. 912-916, Sept. 2008.
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