Author: WaelBadawy
The litigation cycle.
As the litigation can be very complex or very simple is can be modelled to six stages. The stages are Case Initiation, Discovery, Settlement, Pretrial Motions, Trial, Post-Disposition.
For all case types, a trial is the single most time-intensive stage of litigation, encompassing between one-third and one-half of total litigation time in cases that progress all the way through trial. Discovery is the second most time-intensive stage, encompassing between one-fifth and one-quarter of total attorney hours. The remaining litigation stages each required less than 15 percent of total attorney time.
The settlement can happen any stage. An appeal will start as well in stage 1, Discovery may not be as deep as the original cycle.
Activities within each stage is detailed below.
Stage 1: Case initiation
Initial fact investigation; legal research; draft complaint/answer, cross-claim, counterclaim or third-party claim; motion to dismiss on procedural grounds; defenses to procedural motions; meet and confer regarding case scheduling and discovery.
Stage2: Discovery
Draft and file mandatory disclosures; draft/answer interrogatories; respond to requests for production of documents; identify and consult with experts; review expert reports; identify and interview non-expert witnesses; depose opponent’s witnesses; prepare for and attend opponent’s depositions; resolve electronically stored information issues; review discovery/case assessment; resolve discovery disputes.
Stage 3: Settlement
Attend mandatory ADR; settlement negotiations; settlement conferences; draft settlement agreement; draft and file motion to dismiss.
Stage 4: Pre-trial Motions/Applications
Legal research; draft motions in limine; draft motions for summary judgment; answer opponent’s motions; prepare for motion hearings; argue motions.
Stage 5: Trial
Legal research; prepare witnesses and experts; meet with co-counsel (trial team); prepare for voir dire; motion to sequester; prepare opening and closing statements; prepare for direct (and cross) examination; prepare jury instructions; propose findings of fact and conclusions of law; propose orders; conduct trial.
Stage 6: Post-Disposition
Conduct post-disposition settlement negotiations; draft motions for rehearing, JNOV, additur, remittitur, enforce judgment; any appeal activity.
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Disclaimer :
This post is for informational purposes only and does not provide legal advice. Materials on this website are published by Wael Badawy and to provide visitors with free information regarding the laws and policies described. However, this website is not designed for the purpose of providing legal advice to individuals. Visitors should not rely upon information on this website as a substitute for personal legal advice. While we make every effort to provide accurate website information, laws can change and inaccuracies happen despite our best efforts. If you have an individual legal problem, you should seek legal advice from an attorney in your own province/state.
Your broken promises speak about you, but they do not hurt me
Now a day, we meet, we talk, I offer, you promise, and I listen.
Then, I wait, wait and wait, AND you do not perform or deliver.
You do not show up again because you got busy and forgot.
So, I will not go back and review your promises; I will move on.
Your promises were valuable for me, because I believed you care,
And now, I know that I am not on your mind any more.
Your broken promises speak about you.
Your broken promises speak about your commitments.
Your broken promises say “you are interested but not committed”.
But, I am committed and not interested,
So, I have to focus on only committed but not interested,
But I promise that once I am interested, ….
…. I will call you to share our interests with no commitment.
The way you do anything is the way you do everything…
And, I am committed and you are just interested, So,
…. we can not have a business together.
T
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Wael
Hierarchical Adaptive Structure Mesh for Efficient Video Coding
Wael Badawy, “Hierarchical Adaptive Structure Mesh for Efficient Video Coding,” The International Journal on Image and Video Processing, Vol. 17, November 2001
A Multiplication-Free Algorithm and A Parallel Architecture for Affine Transformation
Affine transformation is widely used in image processing. Recently, it is recommended by MPEG-4 for video motion compensation. This paper presents a novel low power parallel architecture for texture warping using affine transformation (AT). The architecture uses a novel multiplication-free algorithm that employs the algebraic properties of the AT. Low power has been achieved at different levels of the design. At the algorithmic level, replacing multiplication operations with bit shifting saves the power and delay of using a multiplier. At the architecture level, low power is achieved by using parallel computational units, where the latency constraints and/or the operating latency can be reduced. At the circuit level, using low power building blocks (such as low power adders) contributes to the power savings. The proposed architecture is used as a computational kernel in video object coders. It is compatible with MPEG-4 and VRML standards. The architecture has been prototyped in 0.6 μm CMOS technology with three layers of metal. The performance of the proposed architecture shows that it can be used in mobile and handheld applications.
Wael Badawy and Magdy Bayoumi, “A Multiplication-Free Algorithm and A Parallel Architecture for Affine Transformation,” The Journal of VLSI Signal Processing-Systems, Kluwer Academic Publishers, Vol. 31, No 2, May 2002, pp. 173-184.
System on Chip: the Future of System Integration
System on chip:
The future of the integration paradigm
Syste`me sur une puce:
le futur du paradigme de l’inte ́gration
Wael Badawy
The increase in the number of transistors that can be integrated on a single chip allows the integration of more functions. On the other hand, time-to-market pressures require novel techniques for developing integrated circuits. System on chip is a methodology that allows the integration of several third-party cores with an embedded processor. This paper presents a tutorial for the system- on-chip methodology and presents the design tasks that are involved in developing a system on chip.
L’accroissement du nombre de transistors qu’il est possible d’inte ́grer sur une puce permet d’offrir plus de fonctionnalite ́s. D’autre part, les pressions de la mise en marche ́ rapide de celles-ci exige l’e ́laboration de techniques nouvelles de de ́veloppement de circuits inte ́gre ́s. Les syste`mes sur une puce repre ́sentent une me ́thodologie de de ́veloppement qui permet l’inte ́gration de com- posantes provenant de plusieurs de ́veloppeurs et de les combiner a` un processeur embarque ́. Cet article pre ́sente un tutoriel sur la me ́thodologie de conception de circuits sur une puce et pre ́sente les taˆches de design implique ́es dans le de ́veloppement de tels syste`mes.
Wael Badawy, “System on Chip: the Future of System Integration,” The Canadian Journal on Electrical and Computer Engineering, Vol. 27, No. 4, October 2002, pp. 149 – 154
A Parallel Multiplication-Free Algorithm and Architecture for Affine-based Motion Compensation
Affine transformation is widely used in image processing. Recently, it has been recommended by MPEG-4 for video motion compensation. We present a novel low-power parallel architecture for texture warping using affine transformation (AT). The architecture uses a novel multiplication-free algorithm that employs the algebraic properties of the affine transformation. Low power has been achieved at different levels of the design. At the algorithmic level, replacing multiplication operations with bit shifting saves the power and delay of using a multiplier. At the architecture level, low power is achieved by using parallel computational units. At the circuit level, using low-power cells contributes to the power savings. The proposed architecture is used as a computational kernel in video object coders. It is compatible with MPEG-4 and virtual reality modeling language (VRML) standards. The architecture has been prototyped in 0.6-µm CMOS technology with three layers of metal. The performance of the proposed architecture shows that it can be used in mobile and handheld applications.
Wael Badawy and Magdy Bayoumi, “A Parallel Multiplication-Free Algorithm and Architecture for Affine-based Motion Compensation,” The SPIE Journal on Optical Engineering, Vol. 42 No. 1, January 2003 pp. 255 – 264
Low power very large scale integration prototype for three-dimensional discrete wavelet transform processor with medical application
We present a low-power 3-D discrete wavelet transform processor for medical applications. The main focus is the compression of medical resonance image (MRI) data, although the system could be used as a generic compression chip. The architecture eliminates redundant filter banks by using a central control unit to dynamically adjust filter parameters. An on-chip cache is used to process block inputs minimizing result throughput. Power consumption has been kept to a minimum by placing constraints throughout the entire design process. The modular processor has been prototyped using 0.6-μm complementary metal oxide semiconductor (CMOS) (three metal) technology. It has been simulated at the functional, circuit, and physical levels. The performance measures of the prototype, area, time delay, power, and utilization have been evaluated. The prototype operates at an estimated frequency of 272 MHz and dissipates 0.5 W of power.
Wael Badawy, Michael Talley, Guoqing Zhang, Michael Weeks, and Magdy Bayoumi, “Low Power Very Large Scale Integration Prototype for Three-Dimensional Discrete Wavelet Transform Processor with Medical Applications,” The SPIE Journal on Electronic Imaging, Vol. 12, Issue 2, April 2003, pp. 270 – 277.
A Low Power Architecture for HASM Motion Tracking
This paper proposes low power VLSI architecture for motion tracking that can be used in online video applications such as in MPEG and VRML. The proposed architecture uses a hierarchical adaptive structured mesh (HASM) concept that generates a content-based video representation. The developed architecture shows the significant reducing of power consumption that is inherited in the HASM concept. The proposed architecture consists of two units: a motion estimation and motion compensation units.
The motion estimation (ME) architecture generates a progressive mesh code that represents a mesh topology and its motion vectors. ME reduces the power consumption since it (1) implements a successive splitting strategy to generate the mesh topology. The successive split allows the pipelined implementation of the processing elements. (2) It approximates the mesh nodes motion vector by using the three step search algorithm. (3) and it uses parallel units that reduce the power consumption at a fixed throughput.
The motion compensation (MC) architecture processes a reference frame, mesh nodes and motion vectors to predict a video frame using affine transformation to warp the texture with different mesh patches. The MC reduces the power consumption since it uses (1) a multiplication-free algorithm for affine transformation. (2) It uses parallel threads in which each thread implements a pipelined chain of scalable affine units to compute the affine transformation of each patch.
The architecture has been prototyped using top-down low-power design methodology. The performance of the architecture has been analyzed in terms of video construction quality, power and delay.
A Low Power Architecture for HASM Motion Tracking
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Wael Badawy and Magdy Bayoumi, “A Low Power VLSI Architecture for Mesh-based Video Motion Tracking,” The Journal of VLSI Signal Processing-Systems, Kluwer Academic Publishers, invited.
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