VLSI architectures Archives - Dr. Wael Badawy https://badawy.ca/tag/vlsi-architectures/ From Idea to Innovation Thu, 22 Feb 2018 18:02:12 +0000 en-US hourly 1 63363634 Architectures for Finite Radon Transform https://badawy.ca/2018/09/18/architectures-for-finite-radon-transform-2/ Tue, 18 Sep 2018 19:23:00 +0000 http://www.badawy.ca/?p=485 Two VLSI architectures for the finite Radon transform are presented. The first is a reference architecture using memory blocks and the second is a memoryless architecture. The proposed architectures use 7×7 size image blocks and are prototyped for processing the CIF image sequence. The simulation and synthesis results show thatRead More

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Two VLSI architectures for the finite Radon transform are presented. The first is a reference architecture using memory blocks and the second is a memoryless architecture. The proposed architectures use 7×7 size image blocks and are prototyped for processing the CIF image sequence. The simulation and synthesis results show that the core speeds of the two proposed architectures are around 100 and 82 MHz, respectively.

Published in:

Electronics Letters  (Volume:40 ,  Issue: 15 )

Page(s):
931 – 932
ISSN :
0013-5194
INSPEC Accession Number:
8068176
DOI:
10.1049/el:20040566
Date of Publication :
22 July 2004
Date of Current Version :
02 August 2004
Issue Date :
22 July 2004
Sponsored by :
Institution of Engineering and Technology
Publisher:
IET

 

C. A. Rahman and W. Badawy, “Architectures for Finite Radon Transform“, The IEE Electronics Letters, Vol. 40, Issue 15, July 2004, pp. 931-932.

 

The post Architectures for Finite Radon Transform appeared first on Dr. Wael Badawy.

]]> 2227 Architectures for Finite Radon Transform https://badawy.ca/2018/05/22/architectures-for-finite-radon-transform/ Tue, 22 May 2018 08:50:00 +0000 http://www.badawy.ca/?p=485 Two VLSI architectures for the finite Radon transform are presented. The first is a reference architecture using memory blocks and the second is a memoryless architecture. The proposed architectures use 7×7 size image blocks and are prototyped for processing the CIF image sequence. The simulation and synthesis results show thatRead More

The post Architectures for Finite Radon Transform appeared first on Dr. Wael Badawy.

]]>

Two VLSI architectures for the finite Radon transform are presented. The first is a reference architecture using memory blocks and the second is a memoryless architecture. The proposed architectures use 7×7 size image blocks and are prototyped for processing the CIF image sequence. The simulation and synthesis results show that the core speeds of the two proposed architectures are around 100 and 82 MHz, respectively.

Published in:

Electronics Letters  (Volume:40 ,  Issue: 15 )

Page(s):
931 – 932
ISSN :
0013-5194
INSPEC Accession Number:
8068176
DOI:
10.1049/el:20040566
Date of Publication :
22 July 2004
Date of Current Version :
02 August 2004
Issue Date :
22 July 2004
Sponsored by :
Institution of Engineering and Technology
Publisher:
IET

 

C. A. Rahman and W. Badawy, “Architectures for Finite Radon Transform“, The IEE Electronics Letters, Vol. 40, Issue 15, July 2004, pp. 931-932.

 

The post Architectures for Finite Radon Transform appeared first on Dr. Wael Badawy.

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