By James O. Hamblen and Michael D. Furman, Kluwer Academic Publishers, 2000.

This book provides an exciting and chal- lenging laboratory component for an un- dergraduate student as well as design engineers working in industry. It intro- duces the field programmable logic device (FPLD) technology and logic synthesis us- ing CAD tools. The book is organized in 13 chapters as follows. Chapter 1 provides a tutorial for CAD tools that covers the de- sign entry, simulation, and hardware im- plementation using an FPLD. Chapter 2 provides an overview of the UP1 FPLD de- velopment board, where the features of the board are briefly described. Chapter 3 introduces the programmable logic tech- nology where the most common complex programmable logic device (CPLD) and field programmable gate array (FPGA) are presented. Chapter 4 is a tutorial to use both a hierarchical and sequential design with different examples. Chapter 5 de- scribes the UP1core library I/O functions. Chapter 6 introduces the use of VHDL for the synthesis of digital hardware. Chapter 7 describes a state machine that controls a virtual electric train system simulation with video output generated directly by the CPLD. Chapter 8 develops a VHDL model of a simple computer where a fetch, decode, and execute cycle is simulated.

CIRCUITS & DEVICES s NOVEMBER 2001

39 s

By James O. Hamblen and Michael D. Furman, Kluwer Academic Publishers, 2000.

This book provides an exciting and chal- lenging laboratory component for an un- dergraduate student as well as design engineers working in industry. It intro- duces the field programmable logic device (FPLD) technology and logic synthesis us- ing CAD tools. The book is organized in 13 chapters as follows. Chapter 1 provides a tutorial for CAD tools that covers the de- sign entry, simulation, and hardware im- plementation using an FPLD. Chapter 2 provides an overview of the UP1 FPLD de- velopment board, where the features of the board are briefly described. Chapter 3 introduces the programmable logic tech- nology where the most common complex programmable logic device (CPLD) and field programmable gate array (FPGA) are presented. Chapter 4 is a tutorial to use both a hierarchical and sequential design with different examples. Chapter 5 de- scribes the UP1core library I/O functions. Chapter 6 introduces the use of VHDL for the synthesis of digital hardware. Chapter 7 describes a state machine that controls a virtual electric train system simulation with video output generated directly by the CPLD. Chapter 8 develops a VHDL model of a simple computer where a fetch, decode, and execute cycle is simulated.

CIRCUITS & DEVICES s NOVEMBER 2001

39 s